Altera Quartus 13.1 Code Above Makes

Altera Quartus 13.1 Code Above Makes

I wont go into details about Verilog in this post, but the code above makes a counter that can be used for frequency divider.

We will also make a simple logic design in Quartus to upload to the CPLD.

This little dev board can be picked up on eBay or Aliexpress for around 10 bucks(including the USB blaster).

Its cheap, easy and simple compared to some of the other FPGA dev boards.

Despite that, I didnt find a lot of tutorials and projects(compared to the Arduino stuff) with this board so I thought Id make a tutorial.

Hardware Used ad MAX II EMP240 CPLD Development Board Documentation Files MAX II CPLD Datasheet Development Board Schematic Software setup First, you will have to download and install Quartus 13.1 (there are other versions that support the MAX II CPLD but I will be using 13.1).

You can find Quartus 13.1 web edition here on Intels website but you will have to make an account and register as a company to be able to download the software(apparently you can just make up a company as they dont really check).

Alternatively, you can go on pirate bay, search for Quartus 13.1 web edition and download it from there.

Check all the boxes, agree to everything, click next without reading, you know the drill;).

I believe that any drivers should get installed automatically so you dont have to worry about that.

Next, connect the ribbon JTAG cable from the USB blaster to the development board.

Usually, the CPLD will already have a blink program uploaded to it, so you should see the top LED starting to blink.

Logic design Making a project First, open up Quartus and start a new project using the project wizard.

Click next. Name your project and set the path to where you want to save it then click next.

Under Available devices select the CPLD that you have on your board.

Just click next. Click finish and we are all done with creating our project.

Making a design We are going to make the Hello World of digital electronics.

We will achieve this using a counter that will act as a frequency divider.

Then we will output the signal to the onboard LED.

Add a new.bdf file: File New Design Files Block DiagramSchematic File.

Open the newly added file(on the left side in the project navigator).

This is going to be our main design file where we implement all the functionality.

Lets add an input and name it CLK as this input will get connected to the onboard(on the actual board not in the CPLD) clock.

In Quartus, we have the option to either draw out discrete logic gates and connect them together or use HDL(hardware definition language).

To create the counter in Verilog first add a new Verilog HDL file like so: select File New Verilog HDL (similar to adding the.bfd file before).

After that paste in the following code.